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Soni, Sunita
- Study of the Soils of Mussoorie Area (Garhwal Himalayas)
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Indian Forester, Vol 115, No 12 (1989), Pagination: 924-933Abstract
Certain soils of Mussoorie forests under Deodar (Cedrus deodara) , Chir (Pinus roxburghii) and Oak (Quercus incana) were studied for their various physical, chemical and physicochemical attributes and classified in to four classes viz, Typic Hapludolls,Typic Dystrochrepts, Typic Argiudolls and Ruptic-Alfic Eutrochrepts. Typic Hapludoll, identified under Deodar and Oak were not much influenced by vegetation whereas Typic Dystrochrepts encountered uDder Deodar and Chir expressed higher order of interaction of vegetation on soil development. The soil development process of Typic Argiudolls found under Deodar were influenced by the vegetative cover in contrast to RuptiC-Alfic Eotrocbrepts under Chir cover.
- Studies on the Optimum Reaction Time for Commercial Cholesterol Kits
Abstract Views :670 |
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Authors
Affiliations
1 Adv V R Manohar Institute of DMLT, Nagpur
2 Consulting Pathologist, Nagpur
3 Institute of Science, Nagpur
1 Adv V R Manohar Institute of DMLT, Nagpur
2 Consulting Pathologist, Nagpur
3 Institute of Science, Nagpur
Source
Asian Journal of Research in Chemistry, Vol 6, No 10 (2013), Pagination: 950-951Abstract
A comparative study on optimum reaction time for four commercial cholesterol kits has been carried out. The kinetics of the reaction mixture has been studied at a concentration of 200mg/dl. It is observed that evaluated concentrations are well within the recommended linearity range as claimed by the manufacturers. As per the claims of the manufacturers the endpoint for all the four kits A,B,C and D is five minutes. The kinetic reaction for Kit D suggests an incomplete reaction since optical density is observed to be climbing beyond recommended end point. Out of all these statistics the % error is most revealing since the % error recorded for kits A,B, C and D is -1.02, 0.66,0.57 and - 9.06 respectively at an extended time of 20 minutes from the initiation of the reaction. It is pertinent to note that it has been mentioned by the manufacturers that the reading can be taken at any time after the manufacturer's recommended end point and before one hour. In this experiment we have recorded readings upto 20 minutes and do not know how it will behave beyond such time. Kits B and C show upward trend whereas kits A and D show the reverse, that is, downward trend. The downward trend is attributed to poor colour stability and there could be variety of reasons which need to be explored.Keywords
Optical Density, Optimum Reaction Time, Cholesterol Kits, End Point, LinearityReferences
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- Generic Approach of Measuring Text Semantic Similarity
Abstract Views :194 |
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Authors
Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
Source
ICTACT Journal on Soft Computing, Vol 12, No 1 (2021), Pagination: 2494-2503Abstract
Text Semantic Similarity can be viewed as one of the challenging tasks as evident from current profound interest in NLP research community that has created achievable milestones through active participation in SemEval task series of the recent decade. Amidst these developments, it was realized that exploring text to compare its semantics largely depends on valid grammatical structures of sentences and sentence formulation types. In this paper, the computation of text semantic similarity is addressed by devising a novel set of generic similarity metrics based on both, word-sense of the phrases constituting the text as well as the grammatical layout and sequencing of these word-phrases forming text with sensible meaning. We have used the combination of word-sense and grammatical similarity metrics over benchmark sentential datasets. Having obtained highest value of Pearson’s correlation coefficient (0.89) with mean human similarity scores, when compared against equivalent scores obtained through closely competent structured approach models, plagiarism-detection classification task was revisited on well-known paragraph-phrased Rewrite corpus articulated by Clough and Stevenson (2011) using our model to provide generic utility perspective to these novel devised similarity metrics. Here also, nearly competent classification model performance (with accuracy 76.8%) encouraged authors to work in directions that are more promising where the performance can be enhanced by improving upon dependency (grammatical relations) component in order to raise the count of true-positives and false-negatives.Keywords
Structural Features, Word-Sense Similarity, Grammatical Similarity, Generic Similarity Metrics, Wikipedia Rewrite Corpus.References
- R. Mihalcea, C. Corley and C. Strapparava, “Corpus-Based and Knowledge Based Measures of Text Semantic Similarity”, Proceedings of American Association for Artificial Intelligence, pp. 775-780, 2006.
- Y. Li, D. McLean, Z.A. Bandar, J.D. O’Shea and K. Crockett, “Sentence Similarity based on Semantic Nets and Corpus Statistics”, IEEE Transactions on Knowledge and Data Engineering, Vol. 18, No. 8, pp. 1138-1145, 2006.
- A. Islam and D. Inkpen, “Semantic Text Similarity using Corpus based Word Similarity and String Similarity”, ACM Transactions on Knowledge Discovery from Data, Vol. 2, No. 2, pp. 1-10, 2008.
- M.C. Lee, “A Novel Sentence Similarity Measure for Semantic based Expert Systems”, Expert Systems with Applications, Vol. 38, No. 5, pp. 6392-6399, 2011.
- D. Gupta, “Detection of Idea Plagiarism using Syntax - Semantic Concept Extractions with Genetic Algorithm”, Expert Systems with Applications, Vol. 73, No. 3, pp. 11-26 ,2017.
- S. Ozates., A. Ozgur and D. Radev, “Sentence Similarity based on Dependency Tree Kernels for Multi-document Summarization”, Proceedings of International Conference on Language Resources and Evaluation, pp. 2833-2838, 2016.
- P. Zhang, X. Huang, L. Zhang, “Information Mining and Similarity Computation for Semi- Un-Structured Sentences from the Social Data”, IEEE Internet of Things, Vol. 34, No. 2, pp. 2352-8648 ,2020.
- S. Alzahrani, M. Salmon and A. Abraham, “An Understanding Plagiarism Linguistic Patterns, Textual Features, and Detection Methods”, IEEE Transactions on Systems, Man, and Cybernetics Part C: Application and Reviews, Vol. 42, No. 2 pp. 133-149,2012.
- Ercan Canhasi, “Measuring the Sentence Level Similarity”, Master Thesis, Department of Computer Science, University of Prizren, pp. 1-42, 2013.
- S. Alzahrani, N. Salim, and V. Palade, “Uncovering Highly Obfuscated Plagiarism Cases using Fuzzy Semantic-Based Similarity Model”, Journal of King Saud University - Computer and Information Sciences, Vol. 27, pp. 248-268, 2015.
- A. Pawar and V. Mago, “Calculating the Similarity between Words and Sentences using a Lexical Database and Corpus Statistics”, IEEE Transactions on Knowledge and Data Engineering, Vol. 18 pp. 1-14, 2018.
- K. Vani and D. Gupta, “A Study on Extrinsic Text Plagiarism Detection Techniques and Tools”, Journal of Engineering Science and Technology, Vol. 9, No. 4, pp. 150-164. 2013.
- S. Alzahrani and N. Salim, “Fuzzy Semantic-Based String Similarity for Extrinsic Plagiarism Detection”, Proceedings of International Conference and Workshop on Multilingual and Multimodal Information Systems, pp. 145-155, 2010.
- M. Potthast, B. Stein, A. Eiselt, A. Barron-Cedeno and P. Rosso, “Overview of the 1st International Competition on Plagiarism Detection.”, Proceedings of International Conference on Spanish Society for Natural Language Processing, pp. 1-69, 2009.
- M. Potthast, B. Stein, A. Eiselt, A. Barron-Cedeno and P. Rosso, “Overview of the 2nd International Competition on Plagiarism Detection”, Proceedings of International Conference on Spanish Society for Natural Language Processing, pp. 1-71, 2010.
- M. Potthast, B. Stein, A. Eiselt, A. Barron-Cedeno and P. Rosso, “Overview of the 3rd International Competition on Plagiarism Detection”, Proceedings of International Conference on Spanish Society for Natural Language Processing, pp. 1-78, 2011.
- M. Potthast, T. Gollub, M. Hagen, J. Grabegger, J. Kiesel, M. Michel, A. Barron-Cedeno and P. Rosso, “Overview of the 4th International Competition on Plagiarism Detection”, Proceedings of International Conference on Spanish Society for Natural Language Processing, pp. 1-68, 2012.
- M. Potthast, T. Gollub, M. Hagen, M. Tippmann, J. Kiesel, P. Rosso, E. Stamatatos and B. Stein, “Overview of the 5th International Competition on Plagiarism Detection”, Proceedings of International Conference on Spanish Society for Natural Language Processing, pp. 1-58, 2013.
- M. Potthast, M. Hagen, B. Anna, B. Matthias, Martin Tippmann, Rosso Paolo and Stein Benno, “Overview of the 6th International Competition on Plagiarism Detection”, Proceedings of International Conference on Spanish Society for Natural Language Processing, pp. 1-66,2014.
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- P. Clough and M. Stevenson, “Developing a Corpus of Plagiarized Short Answers”, Language Resources and Evaluation: Special Issue on Plagiarism and Authorship Analysis, Vol. 45, No. 1, pp. 5-24, 2011.
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- Hardware Security Model With Vedic Multiplier Based Ecc Algorithm On High-performance Fpga Device
Abstract Views :111 |
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Authors
Saurabh Singh
1,
Sunita Soni
1
Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 8, No 1 (2022), Pagination: 1283-1287Abstract
The key problem that the world is most concerned about is security. Data security is the process of preventing unauthorized access to sensitive data. It includes all of the cybersecurity measures you take to keep your data safe from unauthorized access, such as encryption and access restrictions (both physical and digital). Data security has always been of the utmost importance. We utilize cryptographic methods to improve the services of data security. The application of cryptographic algorithms achieves data encryption. Therefore, we developed two versions of ECC algorithms on FPGA for improved hardware security in this study. The FPGA device employed here is Kintex-7, and there are two types of ECC: standard ECC and Vedic multiplier-based ECC. Vedic multiplier-based ECC has discovered that it consumes less space than standard ECC. Not only does Vedic multiplier-based ECC save space, but it also saves electricity. As a result, it is determined that for improved hardware security with ECC enabled, Vedic Multiplier-based ECC should be used over standard ECC.Keywords
ECC, Vedic Multiplier based ECC, Area, Power, and FPGAReferences
- Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Lightweight AES Algorithm Implementation for Encrypting Voice Messages using Field Programmable Gate Arrays”, Journal of King Saud University-Computer and Information Sciences, Vol. 83, pp. 1-18, 2020.
- Aryan Kaushik and Keshav Kumar, “Design and Implementation of Advanced Encryption Standard Algorithm on 7th Series Field Programmable Gate Array”, Proceedings of International Conference on Smart Structures and Systems, pp. 1-3, 2020.
- Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA”, Proceedings of International Conference on Reliability, Infocom Technologies and Optimization, pp. 182-185, 2020.
- Keshav Kumar, K.R. Ramkumar and Amanpreet Kaur, “A Survey on Hardware Implementation of Cryptographic Algorithms Using Field Programmable Gate Array”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 189-194, 2020.
- K. Kumar, S. Malhotra and A. Kumar, “Design of Thermal-Aware and Power-Efficient LFSR on Different Nanometer Technology FPGA for Green Communication”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 236-240, 2021.
- K. Kumar, S. Malhotra and A. Kumar, 2019, "Frequency Scaling Based Low Power Oriya Unicode Reader (OUR) Design ON 40nm and 28nm FPGA”, International Journal of Recent Technology and Engineering, Vol. 7, No. 6, pp. 1-13, 2019.
- Bishwajeet Pandey, Keshav Kumar and Aiza Batool Shabeer Ahmad, “Implementation of Power-Efficient Control Unit on Ultra-Scale FPGA for Green Communication”, 3C Tecnologia, Vol. 10, No. 1, pp. 93-105, 2021.
- Bishwajeet Pandey and Keshav Kumar, “Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA”, International Journal of InnovativeTechnology and Exploring Engineering, Vol. 9, No. 2, pp. 512-514, 2019.
- Keshav Kumar, Amanpreet Kaur, S.N. Panda, “Effect of Different Nano Meter Technology Based FPGA on Energy Efficient UART Design”, Proceedings of International Conference on Communication Systems and Network Technologies, pp. 1-4, 2018.
- C.T. Poomagal, G.A. Sathish Kumar and D. Mehta, “Revisiting the ECM-KEEM Protocol with Vedic Multiplier for Enhanced Speed on FPGA Platforms”, Journal of Ambient Intelligence and Humanized Computing, Vol. 98, pp. 1-11, 2021.
- R.K. Kadu and D.S. Adane, “Hardware Implementation of Efficient Elliptic Curve Scalar Multiplication using Vedic Multiplier”, International Journal of Communication Networks and Information Security, Vol. 11, No. 2, pp. 270-277, 2019.
- P. Ahuja, H. Soni and K. Bhavsar, “Fast, Secure and Efficient Vedic Approach for Cryptographic Implementations on FPGA”, Proceedings of International Conference on Electronics, Communication and Aerospace Technology, pp. 1706-1710, 2018.
- P. Ahuja, H. Soni and K. Bhavsar, “High Performance Vedic Approach for Data Security using Elliptic Curve Cryptography on FPGA”, Proceedings of International Conference on Trends in Electronics and Informatics, pp. 187-192, 2018.
- S. Karthikeyan and M. Jagadeeswari, “Performance Improvement of Elliptic Curve Cryptography System using Low Power, High Speed 16× 16 Vedic Multiplier based on Reversible Logic”, Journal of Ambient Intelligence and Humanized Computing, Vol. 12, No. 3, pp. 4161-4170, 2021.
- R.K. Kodali, S.S. Yenamachintala and L. Boppana, “FPGA Implementation of 160-Bit Vedic Multiplier”, Proceedings of International Conference on Devices, Circuits and Communications, pp. 1-5, 2014.
- T.S. Reddy and Y.D.S.Raju, “Implementation of Data Security with Wallace Tree Approach using Elliptical Curve Cryptography on FPGA”, Turkish Journal of Computer and Mathematics Education, Vol. 12, No. 6, pp. 1546-1553, 2021.
- Effect Of Adder Circuits Over Multiplier Design Based On Vedic Mathematics
Abstract Views :88 |
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Authors
Saurabh Singh
1,
Sunita Soni
1
Affiliations
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
1 Department of Computer Science and Engineering, Bhilai Institute of Technology, IN
Source
ICTACT Journal on Microelectronics, Vol 7, No 4 (2022), Pagination: 1256-1259Abstract
Multiplication is critical for computers linked to cryptography or the ALU function. It consumes more chip area and time than the other ALU functions. The speed of the processor, coprocessor, or embedded system may depend on the multipliers’ speed. Nowadays, designing a small, high-performance multiplier is a critical challenge in computer architecture, cryptographic hardware design, and embedded system design. One of the better solutions is developing a digital multiplier design based on Vedic mathematical formula. The performance of the Digital Vedic Multiplier (DVM) is entirely dependent on the adder network. DVM is evaluated here using KS Adder and CLA Adder. There are several publications on this topic, but the primary shortcoming is that they focus exclusively on the DVM without addressing the influence of the adder circuit. This work aims to investigate the impact of the adder circuit on the space-speed trade-off inherent in the design of the DVM.Keywords
Vedic Mathematics, Digital Vedic Multiplier, Adder, Urdhv Triyagyabhyam, SpeedReferences
- S.B.K. Tirtha and V.S. Agrawala, “Vedic Mathematics”, Motilal Banarsidass Publishers Private Limited, 2013.
- S. Singh, “Design of High-Speed Multiplier using Ancient Indian”, Master Thesis, Department of Electronics, Chhattisgarh Swami Vivekanand Technical University, pp. 1-87, 2009.
- H. Thapliyal and M.B. Srinivas, “High Speed Efficient NxN Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics”, Enformatika, Vol. 2, pp. 225-228, 2004.
- H. Thapliyal and H.R. Arabnia, “A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics”, Proceedings of International Conference on Embedded Systems and Applications, pp. 434-439, 2004.
- H. Thapliyal and M.B. Srinivas, “VLSI Implementation of RSA Encryption System using Ancient Indian Vedic Mathematics”, Proceedings of International Conference on Microtechnologies for the New Millennium, pp. 888-892, 2005.
- A. Singh, “Implementation of 16 Bit Vedic Multiplier”, Master Thesis, Department of Electrical and Electronics Engineering, Thapur University, pp. 1-72, 2010.
- R.K. Bathija, R.S. Meena, S. Sarkar and R. Sahu, “Low Power High Speed 16x16 bit Multiplier using VedicMathematics”, International Journal of Computer Applications, Vol. 59, No. 6, pp. 41-44, 2012.
- M. Pradhan, R. Panda and S.K. Sahu, “Speed Comparison of 16x16 Vedic Multipliers”, International Journal of Computer Applications, Vol. 21, No. 6, pp. 1-14, 2011.
- C. Venkatesan and P. Karthigaikumar, “An Efficient Noise Removal Technique using Modified Error Normalized LMS Algorithm”, National Academy Science Letters, Vol. 41, No. 3, pp. 155-159, 2018.
- S. Kannan, C. Selvaraj and S.N. Mohanty, “Forecasting Energy Generation in Large Photovoltaic Plants using Radial Belief Neural Network”, Sustainable Computing: Informatics and Systems, Vol. 34, No. 2, pp. 1-17, 2021.
- A.R. Suhas and M.M. Priyatham, “Heal Nodes Specification Improvement using Modified Chef Method for Group Based Detection Point Network”, International Journal of Pervasive Computing and Communications, Vol. 33, No. 2, pp. 1-12, 2021.
- M. Ramkumar, R. Manikandan, K.S. Kumar and R.K. Kumar, “Intrusion Detection in Manets using Support Vector Machine with Ant Colony Optimization”, ICTACT Journals on Data Science and Machine Learning, Vol. 1, No. 1, pp. pp. 37-42, 2019.
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- R. Pushpangadan, V. Sukumaran and V. Sundar, “High Speed Vedic Multiplier for Digital Signal Processors”, IETE Journal of Research, Vol. 55, No. 6, pp. 282-286, 2009.
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- V. Kunchigik, L. Kulkarni and S. Kulkarni, “Pipelined Vedic-Array Multiplier Architecture”, International Journal of Image, Graphics and Signal Processing, Vol. 6, No. 6, pp. 58-67, 2014.
- T. Karthikeyan, K. Praghash and K.H. Reddy, “Binary Flower Pollination (BFP) Approach to Handle the Dynamic Networking Conditions to Deliver Uninterrupted Connectivity”, Wireless Personal Communications, Vol. 121, No. 4, pp. 3383-3402, 2021.
- S. Srimani, D.K. Kundu, S. Panda and B. Maji, “Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra”, Proceedings of International Conference on ComputationalAdvancement in Communication Circuits and Systems, pp. 443-449, 2015.
- S. Srimani, D.K. Kundu, S. Panda and B. Maji, “Implementation of Optimized High Performance 4x4 Multiplier using Ancient Vedic Sutra in 45 nm Technology”, Proceedings of International Conference on Devices, Circuits and Systems, pp. 1-6, 2014.
- K.B. Jagannatha, H.S. Lakshmisagar and G.R. Bhaskar, “FPGA and ASIC Implementation of 16-Bit Vedic Multiplier Using Urdhva Triyakbhyam Sutra”, Proceedings of International Conference on Emerging Research in Electronics, Computer Science and Technology, pp. 31-38, 2014.
- H. Sharma, G.K. Jindal, and P.R. Murthy, “Comparison Between Array Multiplier and Vedic Multiplier”, International Journal of Electronics and Communication Engineering and Technology, Vol. 8, No. 3, pp. 1-14, 2014.
- M. Pradhan and R. Panda, “High Speed Multiplier using Nikhilam Sutra Algorithm of Vedic Mathematics”, International Journal of Electronics, Vol. 101, No. 3, pp. 300-307, 2014.
- A. Tiwari and S. Lal, “An Approach Towards the HighEfficient and low Propagation Delay in Digital Processor”, International Journal of Electrical, Electronics and Computer Engineering, Vol. 6, No. 1, pp. 62-70, 2017.
- J. Kumar, K. Selva, and R. Rahim, “Design and UVM Verification of High Speed ALU”, International Journal on Emerging Technologies, Vol. 10, No. 1, pp. 93-96, 2019.
- G.G. Kumar and V. Charishma, “Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques”, International Journal of Scientific and Research Publications, Vol. 2, No. 3, pp. 1-15, 2012.
- R. Santhiya and M.T. Thamaraimanalan, “Power Gating Based Low Power 32 Bit BCD Adder using DVT”, International Journal for Scientific Research and Development, Vol. 3, No. 2, pp. 802-805, 2015.
- R.K. Kodali, S.S. Yenamachintala and L. Boppana, “FPGA Implementation of 160-Bit Vedic Multiplier”, Proceedings of International Conference on Devices, Circuits and Communications, pp. 1-5, 2014.
- C.Venkatesan, P. Karthigaikumar, A. Paul, S. Satheeskumaran and R. Kumar, “ECG Signal Preprocessing and SVM Classifier-Based Abnormality Detection in Remote Healthcare Applications”, IEEE Access, Vol. 6, pp. 9767-9773, 2018.
- K. Praghash and T. Karthikeyan, “An Investigation of Garbage Disposal Electric Vehicles (GDEVs) Integrated with Deep Neural Networking (DNN) and Intelligent Transportation System (ITS) in Smart City Management System (SCMS)”, Wireless Personal Communications, Vol. 124, No. 2, pp. 1-20, 2021